7-Segment Display Interface VHDL Source Code
vhdl
7-segment display
interface
source code
digital design
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This page provides VHDL source code for interfacing with a 7-segment display.
VHDL Code
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity mux_disp1 is
Port (
clk: in std_logic; -- 4MHz clock input
Rst: in std_logic; -- Reset input
seg: out std_logic_vector(6 downto 0); -- 7-segment output
base: out std_logic_vector(3 downto 0) -- Digit select output
);
end mux_disp1;
architecture mux_disp_arch1 of mux_disp1 is
signal count : std_logic_vector(25 downto 0);
signal base_cnt: std_logic_vector(1 downto 0);
signal seg_cnt: std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if rst = '1' then
count <= (others=>'0');
elsif clk='1' and clk'event then
count <= count + '1';
end if;
end process;
base_cnt <= count(12 downto 11);
seg_cnt <= count(25 downto 22);
Base <= "1110" when base_cnt="00" else
"1101" when base_cnt="01" else
"1011" when base_cnt="10" else
"0111" when base_cnt="11" else
"1111";
Seg <= "0111111" when seg_cnt="0000" else --- 0
"0000110" when seg_cnt="0001" else --- 1
"1011011" when seg_cnt="0010" else --- 2
"1001111" when seg_cnt="0011" else --- 3
"1100110" when seg_cnt="0100" else --- 4
"1101101" when seg_cnt="0101" else --- 5
"1111101" when seg_cnt="0110" else --- 6
"0000111" when seg_cnt="0111" else --- 7
"1111111" when seg_cnt="1000" else --- 8
"1100111" when seg_cnt="1001" else --- 9
"1110111" when seg_cnt="1010" else --- A
"1111100" when seg_cnt="1011" else --- B
"0111001" when seg_cnt="1100" else --- C
"1011110" when seg_cnt="1101" else --- D
"1111001" when seg_cnt="1110" else --- E
"1110001" when seg_cnt="1111" else --- F
"0000000";
End mux_disp_arch1;