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1-Bit and 4-Bit Comparator Design in Verilog
This article presents Verilog HDL code for designing 1-bit and 4-bit comparators, including truth tables and simulation results.
Source Code / Verilog
Showing 20 posts (Page 1 of 2)
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2 to 4 Decoder Verilog HDL Code
Verilog HDL code for a 2 to 4 decoder implementation, truth table, and simulation results.
32-bit ALU Verilog Code Implementation
Verilog source code for a 32-bit Arithmetic Logic Unit (ALU) capable of performing arithmetic and logical operations. Includes truth table and simulation results.
4-Bit BCD Asynchronous Reset Counter in Verilog
Verilog code for a 4-bit BCD asynchronous reset counter, including module definition and reset functionality.
4-Bit BCD Synchronous Reset Counter Verilog Code
Verilog source code for a 4-bit BCD synchronous reset counter, block diagram, and truth table for understanding its operation.
4-Bit Binary Asynchronous Reset Counter in Verilog
Verilog code implementation of a 4-bit binary asynchronous reset counter, including block diagram and truth table.
4-Bit Binary Synchronous Reset Counter in Verilog
Verilog code for a 4-bit binary synchronous reset counter, complete with a block diagram and truth table for understanding its operation.
4-Bit Binary to Gray Counter Converter in Verilog
Verilog implementation of a 4-bit binary to Gray code counter converter with symbol, truth table, and simulation results.
4-Bit Down Counter Verilog Code and Test Bench
Verilog code for a 4-bit down counter is presented, along with its corresponding test bench for simulation and verification.
4-bit Mod 13 Counter: Verilog Code and Test Bench
Verilog code for a 4-bit Mod 13 counter with its test bench, including explanations of the code's functionality.
4-to-1 Multiplexer and 1-to-4 Demultiplexer Verilog Code
Verilog HDL code for a 4-to-1 multiplexer and a 1-to-4 demultiplexer, including truth tables and simulation results.
8 to 1 Multiplexer Verilog HDL Code
Verilog HDL code for an 8-to-1 multiplexer, including its symbol, truth table, and simulation results.
8-to-3 Encoder Without Priority: Verilog Code
Verilog source code for an 8-to-3 encoder without priority, including a block diagram and truth table for understanding its functionality.
8-to-3 Priority Encoder: Verilog Code
Verilog code for an 8-to-3 priority encoder, including the truth table, schematic, code explanation, and simulation results.
8-to-3 Priority Encoder: Verilog Code Implementation
Verilog code for an 8-to-3 priority encoder, complete with a block diagram and truth table for understanding its functionality.
Asynchronous FIFO Verilog Code and Test Bench
Verilog code implementation of an Asynchronous FIFO, including a test bench and simulation output analysis.
D Flip-Flop Implementation Without Reset: Verilog Code and Simulation
Explore a D flip-flop implementation without reset, including Verilog code, test bench, simulation results, and RTL schematic.
D Flip-Flop with Synchronous Reset: Verilog Implementation
Explore the Verilog code, test bench, simulation, and RTL schematic of a D flip-flop with synchronous reset.
Full Adder Verilog HDL Code
Verilog HDL implementation of a full adder, including truth table, code, and simulation results.
Low Pass FIR Filter Verilog Implementation
This article presents a Verilog implementation of a low-pass FIR filter using coefficients generated from MATLAB and converted to Q-15 format.
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