Source-Code » VHDL » 4-Bit Braun Multiplier VHDL Code

4-Bit Braun Multiplier VHDL Code

vhdl
multiplier
braun
digital design
source code

This page provides the VHDL source code for a 4-bit Braun multiplier.

VHDL Code

entity braun_multiplier4 is
    port (
        a : in std_logic_vector (3 downto 0);
        b : in std_logic_vector (3 downto 0);
        p : out std_logic_vector (7 downto 0)
    );
end braun_multiplier4;

architecture behavioral of braun_multiplier4 is
    signal s1,s2,s3,s4 : std_logic_vector (3 downto 0);
    signal f1,f2,f3,f4 : std_logic_vector (4 downto 0);

    component and21
        port(
            a : in std_logic;
            b : in std_logic;
            c : out std_logic
        );
    end component;

    component f_adder
        port (
            a : in std_logic;
            b : in std_logic;
            c : in std_logic;
            sum : out std_logic;
            carry : out std_logic
        );
    end component;

begin
    g1: for i in 0 to 3 generate
        a1: and21 port map (b(0), a(i), s1(i));
        p(0) <= s1(0);
    end generate;

    g2: for j in 0 to 3 generate
        a2: and21 port map (b(1), a(j), s2(j));
    end generate;

    fa1: f_adder port map (s1(1), s2(0), '0', p(1), f1(0));
    fa2: f_adder port map (s1(2), s2(1), '0', f1(1), f1(2));
    fa3: f_adder port map (s1(3), s2(2), '0', f1(3), f1(4));

    g3: for k in 0 to 3 generate
        a3: and21 port map (b(2), a(k), s3(k));
    end generate;

    fa4: f_adder port map (s3(0), f1(0), f1(1), p(2), f2(0));
    fa5: f_adder port map (s3(1), f1(2), f1(3), f2(1), f2(2));
    fa6: f_adder port map (s3(2), f1(4), s2(3), f2(3), f2(4));

    g4: for l in 0 to 3 generate
        a3: and21 port map (b(3), a(l), s4(l));
    end generate;

    fa7: f_adder port map (s4(0), f2(0), f2(1), p(3), f3(0));
    fa8: f_adder port map (s4(1), f2(2), f2(3), p(4), f3(2));
    fa9: f_adder port map (s4(2), f2(4), s3(3), f3(3), f3(4));

    fa10: f_adder port map ('0', f3(0), f3(1), p(4), f4(0));
    fa11: f_adder port map (f4(0), f3(2), f3(3), p(5), f4(1));
    fa12: f_adder port map (f4(1), f3(4), s4(3), p(6), p(7));

end behavioral;

VHDL Code for Basic Logic Gates

VHDL source code implementation of basic logic gates, including AND, OR, NOT, NAND, NOR, XOR, and XNOR.

vhdl
logic gates
source code