Source-Code » VHDL » VHDL Code for Basic Logic Gates

VHDL Code for Basic Logic Gates

vhdl logic gates source code digital design hardware description language

This page provides VHDL source code for implementing all basic logic gates.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity gates is
    port (
        a_in, b_in: in std_logic;
        not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op: out std_logic
    );
end gates;

architecture dataflow of gates is
begin
    not_op <= not a_in;
    and_op <= a_in and b_in;
    nand_op <= a_in nand b_in;
    or_op <= a_in or b_in;
    nor_op <= a_in nor b_in;
    xor_op <= a_in xor b_in;
    xnor_op <= a_in xnor b_in;
end ;