4-Bit Binary Synchronous Reset Counter VHDL Code

This page provides VHDL source code for a 4 Bit Binary Synchronous Reset Counter. It also includes the block diagram and truth table.

Block Diagram

Image alt: 4 bit Binary Synchronous Reset Counter Block Diagram

Truth Table

Image alt: 4 bit Binary Synchronous Reset Counter Truth Table

4 Bit Binary Synchronous Reset Counter VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity bin_syn is
    port (
        clk, rst: in std_logic;
        bin_out: out std_logic_vector(3 downto 0)
    );
end bin_syn;

architecture behavioral of bin_syn is
    signal div: std_logic_vector(22 downto 0);
    signal clkdiv: std_logic;
begin
    process (clk)
    begin
        if (rising_edge(clk)) then
            div <= div + '1';
        end if;
    end process;

    clkdiv <= div(22);

    process (clkdiv)
        variable temp: std_logic_vector(3 downto 0) := "0000";
    begin
        if (rising_edge(clkdiv)) then
            if (rst = '1') then
                temp := temp + '1';
            end if;
        end if;
    end process;

    bin_out <= temp;
end ;