T, D, SR, JK Flip-Flop Verilog HDL Code Examples

verilog
hdl
flip flop
digital logic
circuit design

This page covers HDL (Hardware Description Language) code in Verilog for T, D, SR, and JK flip-flops.

T Flip-Flop

Symbol

Here’s the symbol and truth table for a T flip-flop:

T flipflop symbol

Truth Table

RstTClkq
101q
111qb
1XNo positive edgePrevious state
0XX0

Verilog Code

module tff(t, clk, rst, q, qb);
  input t, clk, rst;
  output q, qb;
  reg q, qb;
  reg temp = 0;

  always @(posedge clk, posedge rst) begin
    if (rst == 0) begin
      if (t == 1) begin
        temp = ~temp;
      end else temp = temp;
    end
    q = temp;
    qb = ~temp;
  end
endmodule

Simulation Result

T flipflop simulation result

D Flip-Flop

Symbol

Here’s the symbol and truth table for a D flip-flop:

D flipflop symbol

Truth Table

clkdqqb
X110
1110
1001

Verilog Code

module dff(d, clk, rst, q, qb);
  input d, clk, rst;
  output q, qb;
  reg q, qb;
  reg temp = 0;

  always @(posedge clk, posedge rst) begin
    if (rst == 0)
      temp = d;
    else
      temp = temp;
    q = temp;
    qb = ~temp ;
  end
endmodule

Simulation Result

D flipflop simulation result

SR Flip-Flop

Symbol

Following is the symbol and truth table of SR flipflop.

SR flipflop symbol

Truth Table

rstprClksrqqb
1XXXX01
01XXX10
00100QbpreviousQbprevious
0010101
0011010
0011111

Verilog Code

module srff(s, r, clk, rst, q, qb);
  input s, r, clk, rst;
  output q, qb;
  reg q, qb;
  reg [1:0] sr;

  always @(posedge clk, posedge rst) begin
    sr = {s, r};
    if (rst == 0) begin
      case (sr)
        2'd1: q = 1'b0;
        2'd2: q = 1'b1;
        2'd3: q = 1'b1;
        default: begin end
      endcase
    end else begin
      q = 1'b0;
    end
    qb = ~q;
  end
endmodule

Simulation Result

SR flipflop simulation result

JK Flip-Flop

Symbol

Here’s the symbol and truth table for a JK flip-flop:

JK flipflop symbol

Truth Table

RstClkJKQQb
1100Previous state
110101
111010
1111QbQ
1No +ve edge--Previous state
0---01

Verilog Code

module jkff(j, k, clk, rst, q, qb);
  input j, k, clk, rst;
  output q, qb;
  reg q, qb;
  reg [1:0] jk;

  always @(posedge clk, posedge rst) begin
    jk = {j, k};
    if (rst == 0) begin
      case (jk)
        2'd1: q = 1'b0;
        2'd2: q = 1'b1;
        2'd3: q = ~q;
        default: begin end
      endcase
    end else
      q = 1'b0;
    qb = ~q;
  end
endmodule

Simulation Result

JK flipflop simulation result