Source-Code » Verilog » 2 to 4 Decoder Verilog HDL Code

2 to 4 Decoder Verilog HDL Code

verilog decoder hdl digital logic combinational logic

This page provides the Verilog HDL code for a 2 to 4 decoder.

Symbol

Figure 1 shows the schematic symbol for a 2 to 4 decoder. The truth table is also provided below.

2 to 4 decoder schematic

2 to 4 decoder schematic

Truth Table

ESel1Sel0Y3Y2Y1Y0
1000001
1010010
1100100
1111000
0XX0000

Verilog Code

module dec2_4 (a,b,en,y0,y1,y2,y3);
    input a, b, en;
    output y0,y1,y2,y3;

    assign y0= (~a) & (~b) & en;
    assign y1= (~a) & b & en;
    assign y2= a & (~ b) & en;
    assign y3= a & b & en;

endmodule

Simulation Result

The simulation result is shown in the following image.

2 to 4 decoder simulation result

2 to 4 decoder simulation result