Source-Code » Verilog » 8 to 1 Multiplexer Verilog HDL Code

8 to 1 Multiplexer Verilog HDL Code

verilog multiplexer hdl digital logic mux

This page provides the Verilog HDL code for an 8-to-1 Multiplexer.

Symbol

Below is the symbol of the 8-to-1 Multiplexer.

8 to 1 multiplexer symbol

Truth Table

Here’s the truth table for the 8-to-1 Multiplexer:

Sel2Sel1Sel0Z
000A
001B
010C
011D
100E
101F
110G
111H

Verilog Code

module mux8_1 (
    input [7:0] I,
    input [2:0] S,
    input en,
    output reg y
);

    always @(en, S, I, y)
    begin
        if (en == 1)
        begin
            if (S == 3'b000)
                y = I[0];
            else if (S == 3'b001)
                y = I[1];
            else if (S == 3'b010)
                y = I[2];
            else if (S == 3'b011)
                y = I[3];
            else if (S == 3'b100)
                y = I[4];
            else if (S == 3'b101)
                y = I[5];
            else if (S == 3'b110)
                y = I[6];
            else if (S == 3'b111)
                y = I[7];
        end
        else
            y = 0;
    end

endmodule

Simulation Result

Here’s a simulation result image showing the behavior of the 8-to-1 Multiplexer:

8 to 1 multiplexer simulation result