Source-Code » VHDL » Full Adder VHDL Source Code

Full Adder VHDL Source Code

vhdl
adder
source code
digital logic
full adder

This page presents the VHDL source code for a Full Adder.

The equations for the Full Adder are as follows:

  • Sum (S) = (A) EXOR (B) EXOR (Ci)
  • Carry Out (CO) = (A AND B) OR (B AND Ci) OR (Ci AND A)

VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FA is
    Port(
        a, b, ci : in STD_LOGIC;
        s, co : out STD_LOGIC
    );
end FA;

architecture Behavioral of FA is
begin
    s <= a xor b xor ci;
    co <= (a and b) or (b and ci) or (ci and a);
end behavioral;

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