1x8 Demultiplexer VHDL Source Code

vhdl
demultiplexer
source code
digital logic
hardware description language

This page provides the VHDL source code for a 1x8 demultiplexer (DEMUX).

VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dmux1 is
    port(
        f: in std_logic;
        s: in std_logic_vector(2 downto 0);
        y: out std_logic_vector(7 downto 0)
    );
end dmux1;

architecture behavioral of dmux1 is
begin
    y(0) <= f when s = "000" else '0';
    y(1) <= f when s = "001" else '0';
    y(2) <= f when s = "010" else '0';
    y(3) <= f when s = "011" else '0';
    y(4) <= f when s = "100" else '0';
    y(5) <= f when s = "101" else '0';
    y(6) <= f when s = "110" else '0';
    y(7) <= f when s = "111" else '0';
end behavioral;
Verilog Code for 1 to 4 Demultiplexer

Verilog Code for 1 to 4 Demultiplexer

This article provides Verilog source code for a 1 to 4 DEMUX, accompanied by a block diagram and truth table for enhanced understanding.

verilog
demultiplexer
digital logic
VHDL Code for a 2 to 4 Decoder

VHDL Code for a 2 to 4 Decoder

This article provides VHDL source code for a 2-to-4 decoder, along with a block diagram and truth table for understanding its operation.

vhdl
decoder
2 to 4 decoder

3-to-8 Decoder VHDL Source Code

VHDL source code for a 3-to-8 decoder implementation, demonstrating a basic digital logic circuit.

vhdl
decoder
source code