Source-Code » VHDL » 3-to-8 Decoder VHDL Source Code

3-to-8 Decoder VHDL Source Code

vhdl decoder source code digital logic implementation

This page provides the VHDL source code for a 3-to-8 decoder.

VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder is
    Port (
        s : in STD_LOGIC_VECTOR (2 downto 0);
        y : out STD_LOGIC_VECTOR (7 downto 0)
    );
end decoder;

architecture Behavioral of decoder is
begin
    with s select
        y <= "00000001" when "000",
             "00000010" when "001",
             "00000100" when "010",
             "00001000" when "011",
             "00010000" when "100",
             "00100000" when "101",
             "01000000" when "110",
             "10000000" when "111",
             "00000000" when others;
end behavioral;