Convolutional Encoder VHDL Source Code

This page provides the VHDL source code for a convolutional encoder. This specific convolutional encoder is designed with the following specifications:

• FEC Rate: 1/2
• Constraint Length: 7
• Generator Polynomials:
  • G1 = 171 (octal) for output 1 (X)
  • G2 = 133 (octal) for output 2 (Y)

VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity conv_enc is
    Port ( din       : in  std_logic;     -- Input
           clk       : in  std_logic;     -- Clock
           reset     : in  std_logic;     -- Reset
           valid_in  : in  std_logic;     -- Valid Input
           z         : out std_logic_vector(1 downto 0);  -- Output data
           valid_out : out std_logic                      -- Output valid signal
         );
end conv_enc;

architecture Behavioral of conv_enc is

    signal a : std_logic;
    signal b : std_logic;
    signal c : std_logic;
    signal d : std_logic;
    signal e : std_logic;
    signal f : std_logic;

begin

    process( clk, reset)
    begin
        if reset = '1' then
            a         <= '0';
            b         <= '0';
            c         <= '0';
            d         <= '0';
            e         <= '0';
            f         <= '0';
            z         <= "00";
            valid_out <= '0';
        elsif (clk = '1' and clk'event )then
            valid_out <= valid_in;
            if valid_in = '1' then
                a <= din;
                b <= a;
                c <= b;  -- Delayed the input by 6 clocks
                d <= c;
                e <= d;
                f <= e;
            end if;

            z(1) <= din xor a xor b xor c xor f;  -- 171(octal)
            z(0) <= din xor b xor c xor e xor f;  -- 133(octal)

        end if;
    end process;

end behavioral;