64QAM Modulation VHDL Source Code

This document provides VHDL source code for 64QAM modulation. For a foundational understanding, refer to the modulation basics.

VHDL Code

-- library declaration
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- entity declarattion
entity ROM_test_n is
    port(
        clk       : in  std_logic;       -- clk
        valid_in  : in  std_logic;       -- valid in high then data is valid
        Reset     : in  std_logic;       -- asynchronous active high reset
        Address   : in  std_logic_vector(5 downto 0);  -- 6 bit input
        data_out  : out std_logic_vector(31 downto 0);  -- mapped data real and imag concatenated
        valid_out : out std_logic        -- valid_out high data out is valid
    );
end ROM_test_n;

--architecture declaration
architecture Behav of ROM_test_n is
begin
    -- process to map data
    process(clk, reset)
    begin
        if reset = '1' then
            data_out   <= (others => '0');
            valid_out  <= '0';
        elsif clk = '1' and clk'event then
            if(valid_in = '1')then
                valid_out   <= '1';

                -- Assign value to the data output port base on the address
                case Address(5 downto 3) is
                    -- real data mapping
                    when "000"  => data_out(31 downto 16) <= x"1D80";  --x"0076";
                    when "001"  => data_out(31 downto 16) <= x"09C0";  --x"0027";
                    when "010"  => data_out(31 downto 16) <= x"3140";  --x"00C5";
                    when "011"  => data_out(31 downto 16) <= x"4500";  --x"0114";
                    when "100"  => data_out(31 downto 16) <= x"E280";  --x"FF89";
                    when "101"  => data_out(31 downto 16) <= x"F640";  --x"FFD8";
                    when "110"  => data_out(31 downto 16) <= x"CEC0";  --x"FF3A";
                    when "111"  => data_out(31 downto 16) <= x"BB00";  --x"FEEB";
                    when others => data_out(31 downto 16) <= x"0000";
                end case;

                case Address(2 downto 0) is
                    -- imag data mapping
                    when "000"  => data_out(15 downto 0) <= x"1D80";  --x"0076";
                    when "001"  => data_out(15 downto 0) <= x"09C0";  --x"0027";
                    when "010"  => data_out(15 downto 0) <= x"3140";  --x"00C5";
                    when "011"  => data_out(15 downto 0) <= x"4500";  --x"0114";
                    when "100"  => data_out(15 downto 0) <= x"E280";  --x"FF89";
                    when "101"  => data_out(15 downto 0) <= x"F640";  --x"FFD8";
                    when "110"  => data_out(15 downto 0) <= x"CEC0";  --x"FF3A";
                    when "111"  => data_out(15 downto 0) <= x"BB00";  --x"FEEB";
                    when others => data_out(15 downto 0) <= x"0000";
                end case;
            else
                data_out  <= (others => '0');
                valid_out <= '0';
            end if;
        end if;
    end process;
end architecture;