BPSK Modulation VHDL Source Code

This page provides the VHDL source code for BPSK modulation and includes a link to the BPSK modulation basics. For a fundamental understanding of BPSK modulation, visit the linked resource.

VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Entity Declaration
entity bpsk_mod is
    Port (
        clk                      : in  std_logic;  -- Processing clock
        valid_in                 : in  std_logic;  -- Input valid signal
        data_in                  : in  std_logic;  -- Input data signal
        reset                    : in  std_logic;  -- Asynchronous reset signal
        valid_out                : out std_logic;  -- output valid signal
        data_out_rl, data_out_ig : out std_logic_vector(15 downto 0)  -- real and imaginary part of the output data
    );
end bpsk_mod;

-- Architecture begins here
architecture Behavioral of bpsk_mod is
begin
    process(clk, reset)
    begin
        if (reset = '1') then
            valid_out   <= '0';
            data_out_rl <= (others => '0');
            data_out_ig <= (others => '0');
        elsif(clk'event and clk = '1')then
            if(valid_in = '1') then
                case data_in is
                    when '1'    =>
                        data_out_rl <= x"c000";
                        data_out_ig  <= x"0000";  -- Based on the input generating the
                        valid_out    <= '1';  -- output signals
                    when '0'    =>
                        data_out_rl <= x"4000";
                        data_out_ig  <= x"0000";
                        valid_out    <= '1';
                    when others =>
                        data_out_rl <= x"0000";
                        data_out_ig  <= x"0000";
                        valid_out    <= '1';
                end case;
            else
                valid_out   <= '0';
                data_out_rl <= (others => '0');
                data_out_ig <= (others => '0');
            end if;
        end if;
    end process;
end behavioral;