4 Bit BCD Asynchronous Reset Counter VHDL Code

This page provides VHDL source code for a 4 Bit BCD Asynchronous Reset Counter.

VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;

entity bcd_asyn is
    port (
        clk, rst: in std_logic;
        bcd_out: out std_logic_vector(3 downto 0)
    );
end bcd_asyn;

architecture behavioral of bcd_asyn is
    signal div: std_logic_vector(22 downto 0);
    signal clkdiv: std_logic;
    signal temp: std_logic_vector(3 downto 0);
begin
    process (clk)
    begin
        if rising_edge(clk) then
            div <= div + 1;
        end if;
    end process;

    clkdiv <= div(22);

    process (clkdiv, rst)
    begin
        if (rst = '0' or temp = "1010") then
            temp <= "0000";
        elsif (rising_edge(clkdiv)) then
            temp <= temp + '1';
        end if;
    end process;

    bcd_out <= temp;
end ;