4-Bit Binary Asynchronous Reset Counter VHDL Code

This page provides VHDL source code for a 4-bit binary asynchronous reset counter. It also includes the block diagram and truth table.

Block Diagram

Here’s the block diagram of the 4-bit binary asynchronous reset counter:

Truth Table

The truth table for the 4-bit binary asynchronous reset counter is shown below:

VHDL Code

Below is the VHDL code for the 4-bit binary asynchronous reset counter.

'''vhdl library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity bin_asyn is port ( clk, rst: in std_logic; bin_out: out std_logic_vector(3 downto 0) ); end bin_syn;

architecture behavioral of bin_syn is signal div: std_logic_vector(22 downto 0); signal clkdiv: std_logic; signal temp: std_logic_vector(3 downto 0); begin process (clk) begin if rising_edge(clk) then div <= div + ‘1’; end if; end process;

clkdiv <= div(22);

process (clkdiv, rst)
begin
    if (rst = '0') then
        temp <= "0000";
    elsif (rising_edge(clkdiv)) then
        temp <= temp + '1';
    end if;
end process;

bin_out <= temp;

end ;