RFCarry Select Adder and Carry Skip Adder: VHDL Code and Explanation
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This page describes the Carry Select Adder and Carry Skip Adder combinational logic diagrams, along with their respective VHDL code implementations. We’ll explore different types of adders, focusing on the Carry Select and Carry Skip architectures.
There are several types of adders:
- Ripple Carry Adder or Carry Propagate Adder
- Carry Look Ahead Adder
- Carry Skip Adder
- Manchester Chain Adder
- Carry Select Adder
- Pre-Fix Adder
- Multi-Operand Adder
- Carry Save Adder
- Pipelined Parallel Adder
Both Carry Select and Carry Skip adders are parallel adders, meaning they compute the addition of variable binary strings which can be of the same or different sizes. Let’s examine each in more detail.
Ripple Carry Adder
The Ripple Carry Adder (RCA) is constructed by cascading full adders in series. Each full adder performs the addition of two binary digits at a specific stage. The carry-out of one stage is directly fed as the carry-in to the next stage.
Figure: 4-Bit Ripple Carry Adder
The figure above depicts a 4-bit RCA. It consists of four full adders. Bits are added according to their binary position. Each bit addition generates a sum and a carry. The carry-out is transmitted to the carry-in of the next higher-order bits. The final result is the sum of the four bits plus a carry-out (c4).
Carry Skip Adder
The Carry Skip Adder is essentially a simple Ripple Carry Adder enhanced with a special “skip chain” that speeds up carry propagation. As mentioned above, the addition of two binary digits at any stage i depends on the carry-in Ci , which is the carry-out Ci-1 of the previous stage. To calculate the sum and carry-out Ci+1 of stage i , the carry-in (Ci) needs to be known in advance. However, in certain cases, Ci+1 can be derived without knowing Ci . This is the fundamental idea behind carry skipping.
Carry Select Adder
Figure: 8-bit carry select adder
This type of block Carry Select Adder performs two operations:
- It computes results in parallel.
- It selects the correct result using single-stage or multiple-stage methods.
This approach uses more area to achieve enhanced speed performance.
Carry Select Adders calculate the sum and carry bits for two alternatives: an input carry of “0” and an input carry of “1”. Once the carry-in is available, the correct pre-computed result is chosen to generate the desired output. Here, the sum is correctly outputted as soon as the carry-in is available, without waiting for the carry-in to calculate the sum. This avoids the time taken to compute the sum, resulting in significant speed improvement.
Figure-2 (shown above) illustrates the implementation of an 8-bit Carry-Select Adder with 4-bit sections.
Carry Select Adder VHDL Code
The Carry Select Adder can be implemented in VHDL as shown below. It is composed of four “carry_select4” components, each of which utilizes two “ripple_carry4” components.
library IEEE;
use ieee.std_logic_1164.all;
entity ripple_carry4 is
port(
e, f : in std_logic_vector( 3 downto 0);
carry_in : in std_logic;
S : out std_logic_vector( 3 downto 0);
carry_out : out std_logic
);
end ripple_carry4;
architecture RTL of ripple_carry4 is
begin
process(e, f, carry_in)
variable tempC : std_logic_vector( 4 downto 0 );
variable P : std_logic_vector( 3 downto 0 );
variable G : std_logic_vector( 3 downto 0 );
begin
tempC(0) := carry_in;
for i in 0 to 3 loop
P(i):=e(i) xor f(i);
G(i):=e(i) and f(i);
S(i)<= P(i) xor tempC(i);
tempC(i+1):=G(i) or (tempC(i) and P(i));
end loop;
carry_out <= tempC(4);
end process;
end;
library IEEE;
use ieee.std_logic_1164.all;
entity carry_select4 is
port(
c, d : in std_logic_vector( 3 downto 0);
C_input : in std_logic;
Result : out std_logic_vector( 3 downto 0);
C_output : out std_logic
);
end carry_select4;
architecture RTL of carry_select4 is
component ripple_carry4
port(
e, f : in std_logic_vector( 3 downto 0);
carry_in : in std_logic;
S : out std_logic_vector( 3 downto 0);
carry_out : out std_logic
);
end component;
For S0: ripple_carry4 Use entity work.ripple_carry4(RTL);
For S1: ripple_carry4 Use entity work.ripple_carry4(RTL);
signal SUM0, SUM1 : std_logic_vector( 3 downto 0 );
signal carry0, carry1 : std_logic;
signal zero, one : std_logic;
begin
zero<='0';
one<='1';
S0: ripple_carry4 port map( e=>c, f=>d, carry_in=>zero, S=>SUM0, carry_out=>carry0 );
S1: ripple_carry4 port map( e=>c, f=>d, carry_in=>one, S=>SUM1, carry_out=>carry1 );
Result<=SUM0 when C_input='0' else SUM1 when C_input='1' else "ZZZZ";
C_output<= (C_input and carry1) or carry0;
end;
library IEEE;
use ieee.std_logic_1164.all;
entity carry_select16 is
port(
A, B : in std_logic_vector( 15 downto 0);
C_in : in std_logic;
SUM : out std_logic_vector( 15 downto 0);
C_out : out std_logic
);
end carry_select16;
architecture RTL of carry_select16 is
component carry_select4
port(
c, d : in std_logic_vector( 3 downto 0);
C_input : in std_logic;
Result : out std_logic_vector( 3 downto 0);
C_output : out std_logic
);
end component;
For S0: carry_select4 Use entity work.carry_select4(RTL);
For S1: carry_select4 Use entity work.carry_select4(RTL);
For S2: carry_select4 Use entity work.carry_select4(RTL);
For S3: carry_select4 Use entity work.carry_select4(RTL);
signal tempc1, tempc2, tempc3 : std_logic;
begin
S0: carry_select4 port map( c=>A ( 3 downto 0 ), d =>B ( 3 downto 0 ), C_input=>C_in, Result=>SUM ( 3 downto 0 ), C_output=>tempc1 );
S1: carry_select4 port map( c=>A ( 7 downto 4 ), d =>B ( 7 downto 4 ), C_input=>tempc1, Result=>SUM ( 7 downto 4 ), C_output=>tempc2 );
S2: carry_select4 port map( c=>A ( 11 downto 8 ), d =>B ( 11 downto 8 ), C_input=>tempc2, Result=>SUM ( 11 downto 8 ), C_output=>tempc3 );
S3: carry_select4 port map( c=>A ( 15 downto 12 ), d =>B ( 15 downto 12 ), C_input=>tempc3, Result=>SUM ( 15 downto 12 ), C_output=>C_out );
end;
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