Source-Code » Verilog » 8-to-3 Encoder Without Priority: Verilog Code

8-to-3 Encoder Without Priority: Verilog Code

verilog

encoder

digital logic

source code

combinational logic

This page provides Verilog source code for an 8-to-3 encoder without priority. We’ll also look at the block diagram and truth table to understand how it works.

Block Diagram

Here’s the block diagram for the 8-to-3 encoder without priority:

8 to 3 Encoder Without Priority Block Diagram

Image Alt Text: 8 to 3 Encoder Without Priority Block Diagram

Truth Table

And here’s the truth table that defines the encoder’s behavior:

8 to 3 Encoder Without Priority Truth Table

Image Alt Text: 8 to 3 Encoder Without Priority Truth Table

Verilog Code

Here’s the Verilog code for the 8-to-3 encoder without priority:

module encoder8_3(en, a_in, y_op);
  input en;
  input [7:0] a_in;
  output [2:0] y_op;
  reg [2:0] y_op;

  always @ (a_in,en)
  begin
    if(en==1 )
      y_op = 3'bzzz;
    else
      case (a_in)
        8'b00000001: y_op = 3'b000;
        8'b00000010: y_op = 3'b001;
        8'b00000100: y_op = 3'b010;
        8'b00001000: y_op = 3'b011;
        8'b00010000: y_op = 3'b100;
        8'b00100000: y_op = 3'b101;
        8'b01000000: y_op = 3'b110;
        8'b10000000: y_op = 3'b111;
        default:    y_op = 3'bxxx;
      endcase
  end
endmodule