4-bit Mod 13 Counter: Verilog Code and Test Bench

This document provides the Verilog code for a 4-bit Mod 13 counter and its corresponding test bench.

4-bit Mod 13 Counter Verilog Code

Here’s the Verilog code for a 4-bit Mod 13 counter:

`define TICK #2
module mod13Cntr(clk, reset, Q);
  input clk, reset;
  output [3:0] Q;
  reg [3:0] Q;

  //Behavioral Code for a Mod-13 counter
  always @ (posedge clk) begin
    if (~reset) begin
      if (Q == 4'b1100) begin
        Q <= `TICK 4'b0;
      end else begin
        Q <= `TICK Q+1;
      end
    end
  end

  always @ (posedge reset) begin
    Q <= 4'b0000;
  end
endmodule

Explanation:

• `define TICK #2: Defines a macro TICK for a delay of 2 time units. This helps in controlling the speed of the counter in simulation.
• module mod13Cntr(clk, reset, Q): Declares the module mod13Cntr with clk (clock), reset, and Q (output) as ports.
• input clk, reset: Declares clk and reset as input signals.
• output [3:0] Q: Declares Q as a 4-bit output signal.
• reg [3:0] Q: Declares Q as a 4-bit register to store the counter’s value.
• always @ (posedge clk) begin … end: This block describes the behavior of the counter on the positive edge of the clock.
  • if (~reset) begin … end: Checks if the reset signal is low (active low reset).
  • if (Q == 4’b1100) begin … end: Checks if the current value of Q is 12 (4’b1100). If it is, the counter resets to 0. This makes it a Mod-13 counter.
  • Q <= `TICK 4’b0: Resets the counter to 0 after a delay defined by TICK.
  • else begin Q <= `TICK Q+1; end: If the counter is not at 12, it increments by 1 after a delay defined by TICK.
• always @ (posedge reset) begin … end: This block describes the reset behavior. On the positive edge of the reset signal, the counter is reset to 0.
  • Q <= 4’b0000: Resets the counter to 0.

4-bit Mod 13 Counter Test Bench

The following is the test bench code for the 4-bit Mod 13 counter:

module main;
  reg clk, reset;
  wire [3:0] Q;
  mod13Cntr dnCntr1(clk, reset, Q);

  initial begin
    forever begin
      clk <= 0;
      #5 clk <= 1;
      #5 clk <= 0;
    end
  end

  initial begin
    reset = 1;
    #12 reset = 0;
    #170 reset = 1;
    #12 reset = 0;
  end
endmodule

Explanation:

• module main: Declares the test bench module named main.
• reg clk, reset: Declares clk and reset as register signals to drive the counter.
• wire [3:0] Q: Declares Q as a wire signal to connect to the counter’s output.
• mod13Cntr dnCntr1(clk, reset, Q): Instantiates the mod13Cntr module, naming the instance dnCntr1 and connecting the signals.
• initial begin forever begin … end end: This block generates a clock signal with a period of 10 time units (5 for low and 5 for high).
  • clk <= 0: Sets the clock low.
  • #5 clk <= 1: After a delay of 5 time units, sets the clock high.
  • #5 clk <= 0: After a delay of 5 time units, sets the clock low.
• initial begin … end: This block generates a reset signal. It asserts the reset high initially, then de-asserts it, and then asserts and de-asserts it again to test the reset functionality.
  • reset = 1: Sets the reset high.
  • #12 reset = 0: After a delay of 12 time units, sets the reset low.
  • #170 reset = 1: After a delay of 170 time units, sets the reset high.
  • #12 reset = 0: After a delay of 12 time units, sets the reset low.

This test bench provides a basic stimulus to the counter, including clock and reset signals, allowing you to simulate and verify its functionality. You can add more complex checks and assertions within the test bench to thoroughly test the counter’s behavior.