4 Bit Binary Synchronous Reset Counter Verilog Code
This page of Verilog source code section covers 4 Bit Binary Synchronous Reset Counter Verilog Code. The block diagram and truth table of 4 Bit Binary Synchronous Reset Counter Verilog Code is also mentioned.
Block Diagram of 4 Bit Binary Synchronous Reset Counter
Truth Table of 4 Bit Binary Synchronous Reset Counter
4 Bit Binary Synchronous Reset Counter Verilog Code
module bin_sync( clk, rst, bin_out);
input clk, rst;
output [3:0] bin_out;
reg [3:0] bin_out;
initial
bin_out=4'b0000;
always @ (posedge clk)
begin
div = div+1'b1;
clkdiv = div[22];
end
always @ (posedge clkdiv)
begin
if (rst==1)
bin_out=bin_out+4'b0001;
end
endmodule
input clk, rst;
output [3:0] bin_out;
reg [3:0] bin_out;
initial
bin_out=4'b0000;
always @ (posedge clk)
begin
div = div+1'b1;
clkdiv = div[22];
end
always @ (posedge clkdiv)
begin
if (rst==1)
bin_out=bin_out+4'b0001;
end
endmodule
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