RFTop 10 VHDL, Verilog, and FPGA Interview Questions and Answers
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This article provides a helpful VHDL and Verilog questionnaire, crafted by specialists in the FPGA embedded systems field. These top 10 VHDL, Verilog, and FPGA interview questions and answers will help interviewees confidently navigate job interviews for FPGA programmer positions. These questions are also useful as FPGA viva questions.
Question -1: Write a simple VHDL program for a D Flip-Flop and a D Latch.
Answer -1:
D Flip-Flop (Edge-Triggered)
- A D Flip-Flop stores the input value on the rising edge of the clock signal.
VHDL Code for D Flip-Flop:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_FlipFlop is
Port (
D : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC
);
end D_FlipFlop;
architecture Behavioral of D_FlipFlop is
begin
process (clk, reset)
begin
if reset = '1' then
Q <= '0'; -- Reset the output
elsif rising_edge(clk) then
Q <= D; -- Capture input on rising edge of clock
end if;
end process;
end Behavioral;
D Latch (Level-Sensitive)
- A D Latch is transparent when the enable signal (EN) is high, meaning it follows the input. When EN is low, the output holds the last value.
VHDL Code for D Latch:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_Latch is
Port (
D : in STD_LOGIC;
EN : in STD_LOGIC;
Q : out STD_LOGIC
);
end D_Latch;
architecture Behavioral of D_Latch is
begin
process (D, EN)
begin
if EN = '1' then
Q <= D; -- Transparent when enable is high
end if;
end process;
end Behavioral;
Key Differences:
- D Flip-Flop: Edge-triggered; updates only on the rising edge of the clock.
- D Latch: Level-sensitive; transparent when enable is high.
Question -2: Write a VHDL program for a 4x1 MUX (Multiplexer).
Answer -2:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX4x1 is
Port (
I0, I1, I2, I3 : in STD_LOGIC;
S : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC
);
end MUX4x1;
architecture Behavioral of MUX4x1 is
begin
process (I0, I1, I2, I3, S)
begin
case S is
when "00" => Y <= I0;
when "01" => Y <= I1;
when "10" => Y <= I2;
when "11" => Y <= I3;
when others => Y <= '0';
end case;
end process;
end Behavioral;
Question -3: Write a VHDL code for an 8 to 3 encoder.
Answer -3:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Encoder8to3 is
Port (
I : in STD_LOGIC_VECTOR(7 downto 0);
Y : out STD_LOGIC_VECTOR(2 downto 0)
);
end Encoder8to3;
architecture Behavioral of Encoder8to3 is
begin
process (I)
begin
case I is
when "00000001" => Y <= "000";
when "00000010" => Y <= "001";
when "00000100" => Y <= "010";
when "00001000" => Y <= "011";
when "00010000" => Y <= "100";
when "00100000" => Y <= "101";
when "01000000" => Y <= "110";
when "10000000" => Y <= "111";
when others => Y <= "000";
end case;
end process;
end Behavioral;
Question -4: Write a VHDL program for a 4-bit binary counter (up or down).
Answer -4:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter4bit is
Port (
clk, reset, up_down : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0)
);
end Counter4bit;
architecture Behavioral of Counter4bit is
signal temp_count : STD_LOGIC_VECTOR (3 downto 0) := "0000";
begin
process (clk, reset)
begin
if reset = '1' then
temp_count <= "0000";
elsif rising_edge(clk) then
if up_down = '1' then
temp_count <= temp_count + 1; -- Up Counting
else
temp_count <= temp_count - 1; -- Down Counting
end if;
end if;
end process;
count <= temp_count;
end Behavioral;
Question -5: Explain the FPGA internal Architecture.
Answer -5:
A Field Programmable Gate Array (FPGA) consists of the following components:
- Configurable Logic Blocks (CLBs) : Contain LUTs (Look-Up Tables), flip-flops, and multiplexers for logic implementation.
- Interconnects : Programmable routing paths for connectivity between logic blocks.
- Input/Output Blocks (IOBs) : Provide interfaces for external communication.
- Clocking Resources : Global clock networks distribute timing signals.
- Block RAM (BRAM) : On-chip memory for data storage.
- DSP Blocks : Perform high-speed mathematical operations.
- Configuration Memory : Holds the user-defined logic and reprograms the FPGA at startup.
Question -6: Write a Verilog program for 1-bit and 4-bit comparators.
Answer -6:
module Comparator1bit (
input A, B,
output A_gt_B, A_lt_B, A_eq_B
);
assign A_gt_B = (A > B);
assign A_lt_B = (A < B);
assign A_eq_B = (A == B);
endmodule
module Comparator4bit (
input [3:0] A, B,
output A_gt_B, A_lt_B, A_eq_B
);
assign A_gt_B = (A > B);
assign A_lt_B = (A < B);
assign A_eq_B = (A == B);
endmodule
Question -7: Write Verilog code for a half adder and a full adder logic circuit.
Answer -7:
module HalfAdder (
input A, B,
output Sum, Carry
);
assign Sum = A ^ B;
assign Carry = A & B;
endmodule
module FullAdder (
input A, B, Cin,
output Sum, Carry
);
assign Sum = A ^ B ^ Cin;
assign Carry = (A & B) | (B & Cin) | (A & Cin);
endmodule
Question -8: Explain the difference between a signal and a variable in VHDL.
Answer -8:
Signals are used as interconnects between components and also to store temporary values. Signals can be declared internal to an architecture and are not available external to the architecture.
A variable, much like in other programming languages, is an object whose value can be changed after its creation.
Question -9: Explain the difference between VHDL and Verilog.
Answer -9:
Both VHDL and Verilog are hardware description languages used to develop code targeted for FPGA devices. The syntax in Verilog is similar to C language. VHDL syntax is different and can be more verbose.
Question -10: How do you implement multiply and divide operations with a power of 2 in VHDL or Verilog?
Answer -10:
A left shift operation is equivalent to multiplication by a power of 2, while a right shift operation is equivalent to division by a power of 2. Therefore, these operations can be easily and efficiently implemented using shift operators.
This set of VHDL and Verilog interview questions and answers is useful for both freshers and experienced professionals seeking FPGA programmer positions.
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