Relay to FPGA Interface VHDL Source Code

This page provides the VHDL source code for a Relay to FPGA interface.

VHDL Code

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;

Entity relay1 is
    Port (
        sw  : in  std_logic;
        Rl1 : out std_logic;
        led : out std_logic
    );
End relay1;

Architecture behavioral of relay1 is
Begin
    Rl1 <= sw;  -- Corrected assignment to use the input 'sw'
    Led <= sw;
end behavioral;

XC2S100TQ144-5 Pin Configuration

The following table describes the pin configuration for the XC2S100TQ144-5 FPGA.