DC Motor Control with FPGA: VHDL Source Code

This document provides VHDL source code for interfacing a DC motor with an FPGA.

VHDL Code

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;

Entity dcmotor1 is
    Port (
        start, dir, clk : in std_logic;
        pwm_out         : out std_logic;
        out_dc          : out std_logic_vector(1 downto 0)
    );
end dcmotor1;

architecture dcmotor_a1 of dcmotor1 is
    signal clk1 : std_logic;
    signal div  : std_logic_vector (24 downto 0);
begin
    process (clk, start)
    begin
        if (start = '0') then
            div <= "0000000000000000000000000";
        elsif (clk'event and clk = '1') then
            div <= div + 1;
        end if;
        clk1 <= div(19);
    end process;

    process (clk1)
    begin
        if (clk1'event and clk = '1') then
            if start = '0' then
                out_dc <= "00";
            elsif start = '1' and dir = '1' then
                out_dc <= "10";
                pwm_out <= '1';
            elsif start = '1' and dir = '0' then
                out_dc <= "01";
                pwm_out <= '1';
            end if;
        end if;
    end process;
end dcmotor_a1;

FPGA Pin Assignments (XC2S100TQ144-5)

Explanation

This VHDL code defines an entity dcmotor1 that controls a DC motor based on the input signals:

• start: A signal to initiate motor operation.
• dir: A signal to control the direction of the motor.
• clk: The main clock signal for the FPGA.

The outputs are:

• pwm_out: A PWM signal to control the motor speed (currently always ‘1’ in this implementation).
• out_dc: A 2-bit signal to control the H-bridge (or similar driver) connected to the DC motor.

The architecture dcmotor_a1 implements the logic:

1. Clock Division: A process divides the input clock clk to generate a slower clock clk1. This slower clock is used for controlling the motor logic.

2. Motor Control Logic: Another process, triggered by clk1, controls the out_dc and pwm_out signals based on the start and dir inputs.

   • If start is ‘0’, the motor is stopped (out_dc <= "00").
   • If start is ‘1’ and dir is ‘1’, the motor rotates in one direction (out_dc <= "10").
   • If start is ‘1’ and dir is ‘0’, the motor rotates in the opposite direction (out_dc <= "01").

   The pwm_out signal is currently always set to ‘1’, meaning the motor will run at full speed when active. For speed control, you would need to modify this logic to generate a proper PWM signal with a variable duty cycle.

Important Considerations

• PWM Implementation: The current implementation lacks proper PWM generation for speed control. You’ll need to add logic to vary the duty cycle of the pwm_out signal. This could involve using a counter and comparing its value to a duty cycle value.

• H-Bridge Control: The out_dc signal is meant to control an H-bridge (or similar driver circuit) that drives the DC motor. You must design the H-bridge according to the out_dc logic. Ensure that the H-bridge you use can handle the voltage and current requirements of the DC motor.

• FPGA Pin Assignments: The provided pin assignments are specific to the XC2S100TQ144-5 FPGA. Adjust these according to your specific FPGA and board.

• Clock Frequency: The clock division logic determines the frequency of clk1, which affects how quickly the motor control logic responds. Adjust the divider value (currently div(19)) to achieve the desired control speed.