VHDL Code for Triangular Wave Generation using DAC

This article presents VHDL code for generating a triangular wave using a Digital-to-Analog Converter (DAC).

VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity triwave is
    port(
        clk, rst: in std_logic;
        dac_out: out std_logic_vector(7 downto 0)
    );
end triwave;

architecture Behavioral of triwave is
    signal counter : std_logic_vector(8 downto 0);
    signal div: std_logic_vector(3 downto 0);
    signal clkdiv:std_logic;
begin
    process(clk)
    begin
        if rising_edge(clk) then
            div <= div + '1' ;
        end if;
    end process;

    clkdiv<=div(2);

    process(clkdiv)
    begin
        if (rst='1') then
            counter <= "000000000";
        elsif rising_edge(clkdiv) then
            counter <= counter + '1' ;
        end if;
    end process;

    process(counter) is
    begin
        if(counter(8)='1')then
            dac_out<= not (counter (7 downto 0));
        else
            dac_out<=counter (7 downto 0);
        end if;
    end process;

end behavioral;

Explanation:

The VHDL code defines an entity called triwave with the following ports:

• clk: Clock input.
• rst: Reset input.
• dac_out: 8-bit output to the DAC.

The architecture Behavioral implements the logic for generating the triangular wave. It uses a counter (counter) and a clock divider (div, clkdiv). The clkdiv signal is generated by dividing the input clock clk. The counter increments with each rising edge of clkdiv. When the most significant bit (MSB) of the counter is ‘1’, the output dac_out is the inverted value of the lower 8 bits of the counter. Otherwise, dac_out is simply the lower 8 bits of the counter. This creates the rising and falling slopes of the triangular wave.