D Latch VHDL Source Code

This page provides VHDL source code for a D Latch.

VHDL Code

entity mydlatch1 is
    port (
        signal d, g: in std_logic;
        signal q: out std_logic
    );
end mydlatch1;

architecture behavior of mydlatch1 is
-- rising edge triggered DFF
begin
    process (g, d)
    begin
        if (g = '1') then
            q <= d;
        end if;
    end process;
end behavior;