Terminology » Data Communication » SERDES Basics: Architecture and IP Core Providers

SERDES Basics: Architecture and IP Core Providers

serdes high speed communication data communication serial deserializer

This page covers SERDES basics, SERDES architecture types, and SERDES IP Core developers/providers.

SERDES

SERDES is the short form of Serializer/Deserializer modules used for high-speed communication links.

As shown in Figure 1, both ends of a high-speed link, such as a fiber optic or Ethernet link, use a SERDES device.

SERDES has two functional modules: PISO (Parallel In Serial Out) and SIPO (Serial In Parallel Out). As depicted, it’s basically a transceiver that converts parallel data to serial data, processes it at very high speeds, and then converts it back to a parallel interface at the other end.

There are several advantages to using SERDES. For example, it enables the transmission of huge amounts of data over a single or differential line, which helps reduce the number of data paths as well as the number of pins. This, in turn, reduces complexity, cost, power consumption, and space on the PCB.

SERDES Architecture Types

There are various SERDES architectures available for implementation. The popular ones are based on the following concepts:

  • Parallel Clock
  • Embedded Clock
  • 8b/10b
  • Bit Interleaved

SERDES IP Core Developer/Provider

Following are the companies offering SERDES IP Cores:

  • Terminus Circuits
  • LVDS SerDes IP core from Microtronix
  • Altera Corporation
  • Lattice Semiconductor
  • Xilinx