100 Gigabit Ethernet Physical Layer (100 Gbps Ethernet PHY)

This 100G PHY has the following features:

• Supports full-duplex operation.
• Preserves the 802.3 Ethernet frame format, utilizing the 802.3 MAC layer.
• Maintains the minimum and maximum frame sizes of the current 802.3 standard.
• Supports a bit error rate (BER) >= 10^-12 at the MAC or physical layer service interface.
• Provides appropriate support for optical transport networks.
• Supports a MAC data rate of 100 gigabits per second (100 Gbps).
• Provides physical layer specifications that support 100 gigabit per second operation over the following:
  • At least 40km on Single-Mode Fiber (SMF)
  • At least 10km on SMF
  • At least 100m on OM3 Multi-Mode Fiber (MMF)
  • At least 7m over a copper cable assembly

100G PHY and PCS

As shown in the figure above, the 100G Ethernet PHY layer is composed of sublayers, which include the Reconciliation sublayer, CGMII, PCS (Physical Coding Sublayer), FEC (Forward Error Correction), PMA (Physical Medium Attachment), PMD (Physical Medium Dependent), AN (Auto-Negotiation), and MDI (Medium Dependent Interface).

In this article, we will go through the PCS sublayer and the multirate distribution concept at both the transmit and receive ends of the 100 Gbps Ethernet physical layer.

The MAC layer, which corresponds to Layer 2 of the OSI model, is connected to the medium either using optical fiber or copper cable by an Ethernet PHY device. This PHY device corresponds to Layer 1 of the OSI model. FEC and AN sublayers depend on the physical layer medium.

The transmit PCS, therefore, performs the initial 64B/66B encoding and scrambling on the aggregate channel (at 100 gigabits per second) before distributing 66-bit blocks in a round-robin basis across the multiple lanes.

100 Gigabit Ethernet Multilane Transmitter

Figure 2 depicts a multilane transmitter of a 100G PHY. For 100 Gigabit Ethernet, 20 PCS lanes have been chosen. The number of electrical or optical interface widths supportable in this architecture is equivalent to the number of factors of the total PCS lanes. Hence, 20 PCS lanes support interface widths of 1, 2, 4, 5, 10, and 20 channels/wavelengths.

Figure 2 provides a look at how these 20 PCS lanes are multiplexed over a fiber optic medium. A single pair of fiber cables carries multiple lanes of data at different wavelengths of light. These 20 PCS lanes carry Ethernet frame data. This data is transmitted through the lanes as 64-bit chunks of data with a 2-bit header. This results in 66 bits per block of data.

Each PCS lane is provided with alignment markers. These are periodically inserted once every 16384 blocks. The bandwidth required for these is created by deleting IPG (Interpacket Gap) characters transmitted between the Ethernet frames. An IPG of 1 character is maintained.

This rate adjustment concept maintains a bit rate of 100 Gigabit, as needed by this Ethernet physical layer. As mentioned, multiplexing is done at the bit level, and all the bits from the same PCS lane follow the same electrical as well as optical path. This ensures that data from the PCS lane is received in the correct bit order at the other end of the link.

Let’s understand PCS lane operation at the transmit end:

• Frame data blocks in lane-0 are numbered 0.0, 0.1, 0.2, and in lane-1 are numbered as 1.0, 1.1, 1.2, and so on.
• As mentioned, the first multiplexing takes place, which uses a round-robin process to copy the 20 lanes of PCS data over 10 electrical lines for transmission into the transceiver module.
• The second multiplexing takes place, which also uses the same round-robin process to copy 10 lanes of data onto four lanes for transmission over the medium. Each of these 4 lanes will have an effective data rate of about 25 Gbps. These will make a total of 100 Gbps rate over the 4 lanes.

100 Gigabit Multilane Receiver

Figure 3 depicts a multilane receiver of a 100 Gbps Ethernet PHY. As shown here, data is received over four lanes.

As mentioned, demultiplexing will take place where four lanes of data are received from the optical medium. This data is unpacked onto 10 electrical lanes, and these 10 lanes are then unpacked onto 20 PCS lanes.