CMOS Transistor Logic Circuits Explained

Complementary Metal-Oxide-Semiconductor (CMOS) transistors are the fundamental building blocks of CMOS technology, which is widely used in the design and fabrication of digital integrated circuits. CMOS technology utilizes both n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) to implement various digital logic functions. Here’s an explanation of the key characteristics and operation of CMOS transistors.

CMOS logic gates are built by combining NMOS and PMOS transistors in a complementary manner. When the NMOS transistor is on, the PMOS transistor is off, and vice versa.

NMOS Transistor (n-channel MOSFET)

An NMOS transistor has three terminals: gate (G), source (S), and drain (D). It is made of an n-type semiconductor material (such as silicon). When a voltage (logic high or ‘1’) is applied to the gate, an electric field is created, attracting electrons to form a conductive channel between the source and drain. Electrons flow from the source to the drain when the transistor is on (conducting).

The symbol for an NMOS transistor in circuit diagrams is a triangle pointing towards the source with the gate connected at the apex. In CMOS, a logic high (1) is typically represented by a voltage close to Vdd (supply voltage), and a logic low (0) is represented by a voltage close to GND (ground).

PMOS Transistor (p-channel MOSFET)

A PMOS transistor also has three terminals: gate (G), source (S), and drain (D). It is made of a p-type semiconductor material. When a voltage (logic low or ‘0’) is applied to the gate, an electric field is created, attracting holes (absence of electrons) to form a conductive channel between the source and drain. Holes flow from the source to the drain when the transistor is on.

The symbol for a PMOS transistor in circuit diagrams is a triangle pointing away from the source with the gate connected at the apex. The voltage levels for logic high and low are reversed compared to NMOS. A logic high (1) is represented by a voltage close to GND, and a logic low (0) is represented by a voltage close to Vdd.

CMOS Inverter

CMOS inverters consist of one n-type MOSFET (NMOS) and one p-type MOSFET (PMOS) connected in series. The source of the NMOS is connected to ground (GND), and the source of the PMOS is connected to the supply voltage (Vdd). The gates of the NMOS and PMOS are connected together (in parallel), forming the input, and the output is taken from the common drain node. The output voltage is inverted compared to the input. When the input is low, the output is high, and vice versa.

• Case-1: When the input is logic 0 (ground), the NMOS is off and the PMOS conducts, providing a low resistance path to Vdd.
• Case-2: When the input is logic 1 (Vdd), the PMOS is off and the NMOS conducts, providing a low resistance path to ground.

CMOS AND Gate

A CMOS AND gate consists of multiple series-connected NMOS transistors and parallel-connected PMOS transistors. The inputs are applied to the gates of the NMOS transistors, and the complemented inputs are applied to the gates of the PMOS transistors. The AND gate output is high (Vdd) only when all inputs are high; otherwise, it is low (ground).

The NMOS transistors conduct when all inputs are high (logic 1), providing a low resistance path to ground. The PMOS transistors conduct when any input is low, providing a low resistance path to Vdd.

CMOS NAND Gate

A CMOS NAND gate is essentially the complement of a CMOS AND gate. The series and parallel connections are inverted to create the NAND function.

CMOS OR Gate

The inputs (A and B) are applied to the gates of the NMOS and PMOS transistors, respectively. The inputs are also connected to the input of an inverter (made of a single PMOS and NMOS transistor in series), which generates the complemented inputs (A’ and B’). Two NMOS transistors are used in parallel, with their source terminals connected to the ground (GND) and their drain terminals connected to the output node. Two PMOS transistors are used in series, with their source terminals connected to the supply voltage (Vdd) and their drain terminals connected to the output node.

Let us understand the working of a CMOS OR gate circuit. When at least one input is high (logic 1), the corresponding NMOS transistor conducts, providing a low resistance path to ground. Simultaneously, the corresponding PMOS transistor is off because its gate voltage is low (complemented input is high). The parallel NMOS transistors create a low-resistance path to ground when at least one input is high, pulling the output node low. The output node is connected to the drain terminals of the NMOS transistors and the source terminals of the PMOS transistors. The voltage at the output node is determined by the conducting transistors, and it is low (logic 0) if at least one input is high.

CMOS NOR Gate

A CMOS NOR gate is constructed similarly to a CMOS NAND gate, but with the series and parallel connections inverted, resulting in a NOR function.

CMOS XOR Gate

A basic CMOS XOR gate can be constructed using four NMOS (n-channel MOSFETs) and four PMOS (p-channel MOSFETs) transistors arranged to implement the XOR logic function. The inputs are A and B, and the outputs are X and X’ (complement of X). The XOR gate produces a true output (logic 1) when the number of true inputs is odd.

Output, Y = A * B’ + B * A’

CMOS XNOR Gate

To convert the XOR gate into an XNOR gate, you can introduce inverters to complement the output as needed. An XNOR gate produces a true output when the number of true inputs is even. A basic CMOS XOR gate consists of inputs A and B and outputs X and X’. An inverter is connected to one of the XOR gate outputs. For example, connect an inverter to output X to create X’ (complement of X). The output X’ of XNOR is now connected to the other XOR gate output, creating an XNOR functionality. The XNOR gate output (Y) is taken from the common connection of X and X’.

Output, Y = A * B + A’ * B’

• Case-1: If A and B are both 0 or both 1, the XOR gate produces a 0 at X and a 1 at X’. The inverter then converts the 1 at X’ to 0, making Y (the common output of X and X’) equal to 0, representing a true XNOR output.
• Case-2: If A and B are different (one 0 and one 1), the XOR gate produces a 1 at X and a 0 at X’. The inverter then converts the 0 at X’ to 1, making Y equal to 1, representing a false XNOR output.

Conclusion

CMOS transistors are crucial components in CMOS technology, offering low power consumption, high noise margins, and versatility for the design of digital integrated circuits. The complementary operation of NMOS and PMOS transistors forms the basis for the efficiency and reliability of CMOS circuits. We’ve explored CMOS logic gate circuits such as inverters, NAND, AND, NOR, OR, XOR and XNOR.