Radix-4 Butterfly VHDL Source Code

vhdl
radix-4
butterfly
fft
signal processing

This page provides the VHDL source code for a Radix-4 butterfly implementation.

VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

entity radix4_butterfly_r is
    port(
        clk   : in  std_logic;                       -- Processing clock
        reset : in  std_logic;                       -- Asynchronous reset signal
        ri0   : in  std_logic_vector(15 downto 0);   -- input1 real part
        ri1   : in  std_logic_vector(15 downto 0);   -- input2 real part
        ri2   : in  std_logic_vector(15 downto 0);   -- input3 real part
        ri3   : in  std_logic_vector(15 downto 0);   -- input4 real part
        ii0   : in  std_logic_vector(15 downto 0);   -- input1 imaginary part
        ii1   : in  std_logic_vector(15 downto 0);   -- input2 imaginary part
        ii2   : in  std_logic_vector(15 downto 0);   -- input3 imaginary part
        ii3   : in  std_logic_vector(15 downto 0);   -- input4 imaginary part
        co1   : in  std_logic_vector(15 downto 0);   -- Cos of the angle1
        co2   : in  std_logic_vector(15 downto 0);   -- Cos of the angle2
        co3   : in  std_logic_vector(15 downto 0);   -- Cos of the angle3
        si1   : in  std_logic_vector(15 downto 0);   -- Sin of the angle1
        si2   : in  std_logic_vector(15 downto 0);   -- Sin of the angle2
        si3   : in  std_logic_vector(15 downto 0);   -- Sin of the angle3
        ro0   : out std_logic_vector(15 downto 0);   -- real part of the output1
        ro1   : out std_logic_vector(15 downto 0);   -- real part of the output2
        ro2   : out std_logic_vector(15 downto 0);   -- real part of the output3
        ro3   : out std_logic_vector(15 downto 0);   -- real part of the output4
        io0   : out std_logic_vector(15 downto 0);   -- imaginary part of the output1
        io1   : out std_logic_vector(15 downto 0);   -- imaginary part of the output2
        io2   : out std_logic_vector(15 downto 0);   -- imaginary part of the output3
        io3   : out std_logic_vector(15 downto 0)    -- imaginary part of the output4
    );
end radix4_butterfly_r;

architecture Behavioral of radix4_butterfly_r is

    --real signals
    signal r1               : std_logic_vector(15 downto 0);
    signal r2               : std_logic_vector(15 downto 0);
    signal r3               : std_logic_vector(15 downto 0);
    signal r4               : std_logic_vector(15 downto 0);
    signal r5               : std_logic_vector(15 downto 0);
    signal t1               : std_logic_vector(15 downto 0);
    signal t3               : std_logic_vector(15 downto 0);
    signal sig_ro2          : std_logic_vector(31 downto 0);
    signal sig_ro1          : std_logic_vector(31 downto 0);
    signal sig_ro3          : std_logic_vector(31 downto 0);

    --imag signals
    signal s1               : std_logic_vector(15 downto 0);
    signal s2               : std_logic_vector(15 downto 0);
    signal s3               : std_logic_vector(15 downto 0);
    signal s4               : std_logic_vector(15 downto 0);
    signal s5               : std_logic_vector(15 downto 0);
    signal t2               : std_logic_vector(15 downto 0);
    signal t4               : std_logic_vector(15 downto 0);
    signal sig_io2          : std_logic_vector(31 downto 0);
    signal sig_io1          : std_logic_vector(31 downto 0);
    signal sig_io3          : std_logic_vector(31 downto 0);

    signal co11, co21, co31 : std_logic_vector(15 downto 0);
    signal si11, si21, si31 : std_logic_vector(15 downto 0);
    signal co12, co22, co32 : std_logic_vector(15 downto 0);
    signal si12, si22, si32 : std_logic_vector(15 downto 0);

    signal mull_r3_co2      : std_logic_vector(31 downto 0);
    signal mull_s3_si2      : std_logic_vector(31 downto 0);
    signal mull_s3_co2      : std_logic_vector(31 downto 0);
    signal mull_r3_si2      : std_logic_vector(31 downto 0);

    signal mull_r4_co1      : std_logic_vector(31 downto 0);
    signal mull_s4_si1      : std_logic_vector(31 downto 0);
    signal mull_s4_co1      : std_logic_vector(31 downto 0);
    signal mull_r4_si1      : std_logic_vector(31 downto 0);

    signal mull_r5_co3      : std_logic_vector(31 downto 0);
    signal mull_s5_si3      : std_logic_vector(31 downto 0);
    signal mull_s5_co3      : std_logic_vector(31 downto 0);
    signal mull_r5_si3      : std_logic_vector(31 downto 0);

    signal ro01             : std_logic_vector(15 downto 0);
    signal io01             : std_logic_vector(15 downto 0);

begin

    process(clk, reset)
    begin
        if reset = '1' then
            r1 <= (others => '0');
            r2 <= (others => '0');
            t1 <= (others => '0');
            s1 <= (others => '0');
            s2 <= (others => '0');
            t2 <= (others => '0');
            t4 <= (others => '0');
            t3 <= (others => '0');
        elsif clk = '1' and clk'event then
            r1 <= ri0 +ri2;
            r2 <= ri0 -ri2;
            t1 <= ri1 +ri3;
            s1 <= ii0 +ii2;
            s2 <= ii0 -ii2;
            t2 <= ii1 +ii3;
            t4 <= ii1 -ii3;
            t3 <= ri1 - ri3;
        end if;
    end process;

    process(clk, reset)
    begin
        if reset = '1' then
            r3          <= ( others => '0');
            s3          <= ( others => '0');
            r4          <= ( others => '0');
            r5          <= ( others => '0');
            s4          <= ( others => '0');
            s5          <= ( others => '0');
            co11        <= ( others => '0');
            co21        <= ( others => '0');
            co31       <= ( others => '0');
            si11       <= ( others => '0');
            si21       <= ( others => '0');
            si31       <= ( others => '0');
            co12       <= ( others => '0');
            co22       <= ( others => '0');
            co32       <= ( others => '0');
            si12       <= ( others => '0');
            si22        <= ( others => '0');
            si32        <= ( others => '0');
            ro0         <= ( others => '0');
            io0         <= ( others => '0');
            mull_r3_co2 <= ( others => '0');
            mull_s3_si2 <= ( others => '0');
            mull_s3_co2 <= ( others => '0');
            mull_r3_si2 <= ( others => '0');
            mull_r4_co1 <= ( others => '0');
            mull_s4_si1 <= ( others => '0');
            mull_s4_co1 <= ( others => '0');
            mull_r4_si1 <= ( others => '0');
            mull_r5_co3 <= ( others => '0');
            mull_s5_si3 <= ( others => '0');
            mull_s5_co3 <= ( others => '0');
            mull_r5_si3 <= ( others => '0');
            ro01        <= ( others => '0');
            io01        <= ( others => '0');
        elsif rising_edge(clk) then
            r3          <= r1 -t1;
            s3          <= s1 -t2;
            r4          <= r2 - t4;
            r5          <= r2 + t4;
            s4          <= s2 + t3;
            s5          <= s2 - t3;
            co11        <= co1;
            co21        <= co2;
            co31        <= co3;
            si11        <= si1;
            si21        <= si2;
            si31        <= si3;
            co12        <= co11;
            co22        <= co21;
            co32        <= co31;
            si12        <= si11;
            si22        <= si21;
            si32        <= si31;
            ro01        <= r1 + t1;
            io01        <= s1 + t2;
            ro0         <= ro01;
            io0         <= io01;
            mull_r3_co2 <= r3*co22;
            mull_s3_si2 <= s3*si22;
            mull_s3_co2 <= s3*co22;
            mull_r3_si2 <= r3*si22;
            mull_r4_co1 <= r4*co12;
            mull_s4_si1 <= s4*si12;
            mull_s4_co1 <= s4*co12;
            mull_r4_si1 <= r4*si12;
            mull_r5_co3 <= r5*co32;
            mull_s5_si3 <= s5*si32;
            mull_s5_co3 <= s5*co32;
            mull_r5_si3 <= r5*si32;
        end if;
    end process;

    --real operation for ro2
    sig_ro2 <= (mull_r3_co2)+(mull_s3_si2);
    ro2     <= sig_ro2(23 downto 8);

    --imag operation for io2
    sig_io2 <= (mull_s3_co2)-(mull_r3_si2);
    io2     <= sig_io2(23 downto 8);

    sig_ro1 <= (mull_r4_co1)+(mull_s4_si1);
    ro1     <= sig_ro1(23 downto 8);

    --imag operation for io1
    sig_io1 <= (mull_s4_co1)-(mull_r4_si1);
    io1     <= sig_io1(23 downto 8);

    --real operation for ro3
    sig_ro3 <= (mull_r5_co3)+(mull_s5_si3);
    ro3     <= sig_ro3(23 downto 8);

    --imag operation for io3
    sig_io3 <= (mull_s5_co3)-(mull_r5_si3);
    io3     <= sig_io3(23 downto 8);

end behavioral;