2-bit Serial to Parallel Conversion in VHDL

This document presents the VHDL source code for a 2-bit serial to parallel converter. It also provides a link to the corresponding 2-bit parallel to serial conversion code.

VHDL Code

-- library declaration
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- entity declaration
entity SIPO_2_n is
    port(
        CLK         : in  STD_LOGIC;                     -- global clk
        D_IN        : in  STD_LOGIC;                     -- serial data in
        EN          : in  STD_LOGIC;                     -- enable
        RESET       : in  STD_LOGIC;                     -- asynchronous reset
        D_OUT       : out STD_LOGIC_VECTOR(1 downto 0);  -- parallel data out
        valid_out   : out std_logic                      -- valid out
    );
end SIPO_2_n;

-- architecture declaration
architecture SIPO4_2_ARCH of SIPO_2_n is
    signal dout_i :     std_logic;
    signal tog    :     std_logic;
begin
    -- process to convert serial to parallel data
    process (clk, reset)
    begin
        if reset = '1' then
            valid_out   <= '0';
            tog         <= '0';
            dout_i      <= '0';
            D_out       <= "00";
        elsif rising_edge(clk) then
            if en = '1' then
                tog  <= not tog;
            else
                tog  <= '0';
            end if;
            dout_i <= D_IN;
            if tog = '1' then
                D_OUT     <= dout_i & D_in;
                valid_out <= '1';
            elsif tog = '0' then
                valid_out <= '0';
            end if;
        end if;
    end process;
end SIPO4_2_ARCH;

Code Explanation

The VHDL code defines an entity SIPO_2_n that implements a 2-bit Serial-In Parallel-Out (SIPO) shift register. Here’s a breakdown:

• Libraries: The code starts by declaring the necessary IEEE libraries for standard logic and unsigned arithmetic.

• Entity Declaration: The entity block defines the input and output ports of the SIPO register:

  • CLK: Clock input signal.
  • D_IN: Serial data input signal.
  • EN: Enable signal. When high, data shifts in.
  • RESET: Asynchronous reset signal. Resets the register to its initial state.
  • D_OUT: 2-bit parallel data output signal.
  • valid_out: Indicates when the output data is valid.

• Architecture Declaration: The architecture block defines the behavior of the SIPO register.

  • Internal Signals: dout_i stores the previous input data bit, and tog is a toggle signal used for controlling when the new parallel output is valid.
  • Process: A sequential process is used to implement the shift register logic. This process is sensitive to the clock (clk) and reset (reset) signals.
    • Reset Condition: If reset is high (‘1’), the output valid_out, the toggle signal tog, the internal data signal dout_i, and the parallel output D_out are all reset to ‘0’ or “00”.
    • Clocked Logic: On the rising edge of the clock (rising_edge(clk)), the following happens:
      • Enable Check: If en is high (‘1’), the tog signal toggles. Otherwise, it is set to ‘0’.
      • Data Shifting: The current D_IN value is stored in dout_i.
      • Parallel Output and Validity: If tog is ‘1’, D_OUT is assigned the concatenated value of dout_i and the current D_in, effectively creating the 2-bit parallel output. valid_out is then set to ‘1’. If tog is ‘0’, valid_out is ‘0’, indicating the output is not yet valid.