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SoC Basics: Understanding System on a Chip Design

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This article introduces the basics of System on a Chip (SoC), including the SoC execution flow. We’ll explore what constitutes an SoC and the steps involved in taking a chip from its initial architecture to the point where SoC samples are available.

What is an SoC (System on a Chip)?

An SoC is essentially an Integrated Circuit (IC) where the entire system is fully integrated onto a single die. It’s a combination of a general-purpose processor, specialized hardware accelerators, various peripheral interfaces, and on-chip storage devices, all working together as a unified system.

Packaging and Connecting the Die to Pins

The way the silicon die is packaged and connected to the outside world significantly impacts its performance and capabilities. Two common methods are:

Wire Bond:

  • Uses thin wires to connect the die to the package pins.
  • Wires introduce resistance and inductance.
  • This can create limitations on high-frequency interfaces.
  • There are physical limitations on the number of wires that can be used.

Flip Chip:

  • Directly connects the die to the package using solder bumps.
  • Offers low resistance and negligible inductance due to direct contact.
  • Suitable for high-frequency interfaces.
  • Allows for a large number of connections/interfaces.
  • Contacts can be placed in the middle of the die image, offering more flexibility in design.

SoC Execution Flow

SoC Execution Flow Image alt: SoC Execution Flow

Design Abstraction Levels

The SoC design process involves several levels of abstraction:

  • Lexical Coding or Behavioral Design, Functional Level- System Level, Algorithmic Level, RTL Level: This is the highest level, where the system’s behavior is described using programming languages or hardware description languages (HDLs).

  • Netlist with Standard Cells - Gate Level: The RTL code is synthesized into a gate-level netlist, representing the circuit using standard logic gates.

  • Typically used by Analog Designers - Transistor Level: At this level, the circuit is described in terms of individual transistors and their connections. Analog designers often work at this level to optimize performance.

  • Mask output of Physical Design - Custom/Layout Level: This is the lowest level, representing the physical layout of the chip, including the placement of transistors and the routing of wires.

Execution Flow Design Levels

SoC Execution flow phases Image alt: SoC Execution flow phases

Steps Involved in the SoC Design Flow

The following steps are generally involved in the SoC design flow:

  • System-level algorithm design: Based on the desired specifications, the system’s functionality is defined and algorithms are developed.

  • Register Transfer Level (RTL) Coding: The algorithms are translated into hardware description language (HDL) code, typically using RTL (Register Transfer Level) or DFT (Design for Testability) techniques.

  • Gate Level Synthesis: The RTL code is synthesized into a gate-level netlist, which describes the circuit in terms of logic gates.

  • Schematic Level (Place and Route): This involves placing the logic gates on the chip and routing the connections between them, resulting in the layout.

  • Silicon Output: Finally, the layout is used to fabricate the physical silicon chip.