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Convolutional Encoder Example and Pseudo Code

convolutional encoder forward error correction channel coding viterbi decoding coding rate

This page describes a convolutional encoder example and provides pseudo code for convolutional encoding. The example considers the code rate, constraint length, and generator polynomials for implementation.

Let’s delve into a Convolutional Encoder example based on the following specifications:

Convolution Encoder (3, 1, 4) Specifications

  • Coding rate: 1/3
  • Constraint length: 5
  • Output bit length: 3
  • Message bit length: 1
  • Maximal memory order / no. of memory elements: 4
  • Generator Polynomials: 25 (octal), 33 (octal), 37 (octal)

Description:

Forward error correction (FEC) enhances channel capacity by introducing carefully designed redundant information to the data transmitted through the channel. This process of adding redundancy is known as channel coding. Convolutional codes operate on serial data, processing one or a few bits at a time.

Convolutional encoding combined with Viterbi decoding is a FEC technique particularly well-suited for channels primarily affected by Additive White Gaussian Noise (AWGN).

Convolutional codes are usually described using two parameters:

  • Code rate
  • Constraint length

The code rate = k/n, represents the ratio of the number of bits entering the convolutional encoder (k) to the number of channel symbols output by the encoder (n) in a given cycle.

The constraint length parameter, K, indicates the “length” of the convolutional encoder, representing how many k-bit stages are available to feed the combinatorial logic producing the output symbols.

The parameter ‘m’ is closely related to K and indicates how many encoder cycles an input bit is retained and used for encoding after its initial input to the encoder. ‘m’ can be viewed as the memory length of the encoder.

Here, we focus on a rate 1/3 convolutional code. Viterbi decoding offers the advantage of a fixed decoding time, making it suitable for hardware implementation. However, its computational demands increase exponentially with the constraint length, typically limiting its practical use to constraint lengths of K = 9 or less.

Input raw binary data is encoded by the binary convolutional encoder, which has a native rate of 1/3 and a constraint length of 5. It uses the following generator polynomials to derive its three code bits (X1, X2, and X3): 25 (octal), 33 (octal), and 37 (octal).

Convolutional Encoder Example

The generator part of the Convolutional encoder is illustrated in the following figure:

convolutional encoder example

Pseudo Code

Convolutional encoding is performed using a shift register and associated combinatorial logic that executes modulo-two addition. (A shift register is a chain of flip-flops where the output of the nth flip-flop is connected to the input of the (n+1)th flip-flop. With each active clock edge, the flip-flop input is clocked through to the output, shifting the data by one stage.)

The octal numbers (25)8, (33)8, and (37)8 represent the code generator polynomials, which when read in binary (10101)2, (11011)2, and (11111)2 correspond to the shift register connections to the upper and lower modulo-two adders as shown in the figure above.

The following steps are taken while designing a convolutional encoder:

  1. Initialize the Memory Registers with zeros on reset: m1=0, m2=0, m3=0, m4=0
  2. Store the incoming bit in memory register m_in: m_in = data_in
  3. After the input bit arrives and the data in is valid, the operation starts and the output is calculated as:
    • x1 = m_in + m2 + m4;
    • x2 = m_in + m1 + m3 + m4;
    • x3 = m_in + m1 + m2 + m3 + m4;
  4. Perform shifting operation:
    • m4 = m3;
    • m3 = m2;
    • m2 = m1;
    • m1 = m_in;
  5. Repeat steps 2, 3, and 4 for the length of the input data bits.

VHDL Source code

For K=7, rate=1/2, G1=171(octal), G2 = 133(octal), Check VHDL code at following page: