DSP Architecture: Algorithm Porting Guide

This DSP tutorial explores the factors involved in implementing a DSP algorithm to suit a particular DSP architecture. It covers concepts like Multipliers, Barrel Shifters, MAC Units, ALUs, On-chip Memory, Parallelism, and Pipelining.

DSP is widely used in baseband development for wireless technologies such as WiMAX, LTE, and WLAN (11ac, 11ad, etc.). A typical DSP should have on-chip registers to store variables, data, and intermediate results. It will also feature on-chip memory or an external memory interface to store input and output signal vectors. Similarly, it will have on-chip program memory or external memory to store the code/program and constant data. DSP algorithms usually need to operate at high speeds and provide accurate results to meet system requirements in modern complex communication systems like LTE, WiMAX, and CDMA.

To achieve this, the following modifications/changes are often required in DSP architecture to optimize efficiency:

1. Multiplier

Parallel and array multipliers are commonly designed for DSP applications. Speed, accuracy, and dynamic range are critical considerations during their design.

2. Barrel Shifter

Normally, shifting one bit either left or right requires one clock cycle. This approach consumes a significant number of cycles for multiple bit shifts. To address this, DSPs often utilize a special type of shifter known as a barrel shifter. This shifter can shift multiple bits in a single instruction cycle, dramatically reducing the number of cycles required.

3. MAC Unit

A MAC (Multiply-Accumulate) unit is designed to perform both multiplication and accumulation operations in a single instruction cycle, effectively executing these operations in parallel. For example, to carry out 512 MAC operations, 513 execution cycles are needed. If one MAC unit takes 100 nanoseconds, the total time required would be approximately:

$513 \times 100 \times 10^{-9} = 51.3 \text{ microseconds}$

4. ALU

The Arithmetic Logic Unit (ALU) is specifically designed for DSP operations, taking into account overflow, underflow, and sign considerations. Special addressing modes such as circular addressing and bit-reversed addressing are utilized in DSP algorithms. Circular addressing is used to manage continuous streams of time-domain signals in a circular buffer, which is common in baseband receiver chains. Bit-reversed addressing is used in the implementation of IFFT/FFT algorithms within complex communication baseband transmitter/receiver designs.

5. DSP Architecture for Bus and Memory

For example, consider the need to execute the following instruction in a single cycle:

ADD A, B

To map and execute this instruction in a single cycle, the DSP needs to have separate program and two data memories with their own separate address/data buses. This allows the DSP to fetch and execute the instruction in a single instruction cycle.

6. On-Chip Memory

On-chip program memory will be faster than off-chip memory. Off-chip memory requires de-multiplexing of the address/data bus when accessing code/data from external memory, which introduces delays.

7. Parallelism

Parallelism refers to the availability of multiple functional units (arithmetic units), allowing computations on addresses and data to be performed by separate units in parallel. Another example is the design of MAC hardware, optimized for speed. The number of MAC units used is often carefully chosen to reduce the cycle count for code execution.

8. Pipelining

Pipelining refers to the parallel execution of instructions, speeding up program execution.

Key Parameters for Algorithm Mapping

The following parameters should be determined for each algorithm to decide which DSP architecture is best suited for mapping the DSP algorithm under development:

1. SNR range within which the algorithm works best.
2. Input and output data rate.
3. Memory size for data/variables.
4. Processing time or latency.
5. Code size or program size.
6. Power consumption of the module in ASIC flow.
7. Type of operations (Arithmetic and logical).
8. Multiply and Accumulate operation.
9. Scaling of the signal (i.e., up-sampling or down-sampling).