ARM and RISC Basics: Understanding the Differences

This tutorial explores the fundamentals of ARM (Advanced RISC Machine) and RISC (Reduced Instruction Set Computing) architectures, highlighting the key differences between them.

ARM History and Introduction

• ARM stands for Advanced RISC Machine.
• It was first developed at Acorn Computer Limited of Cambridge between 1983 and 1985.
• ARM Limited was formed in 1990.
• ARM is a leading producer of 16/32-bit embedded RISC machines.
• ARM licenses its core designs to semiconductor manufacturers and does not produce integrated circuits (ICs) themselves.
• It is based on the RISC architecture.
• ARM processors offer high code density, low power consumption, and a small silicon area.
• It employs a load-store architecture, where data processing occurs through registers, avoiding direct memory modifications.
• ARM offers a good speed-to-power consumption ratio.

RISC Features

• Instructions: RISC architectures utilize a smaller instruction set compared to CISC (Complex Instruction Set Computing). The compiler or programmer combines several simple instructions to synthesize more complex operations (e.g., division). Each instruction has a fixed length, allowing the pipeline to fetch subsequent instructions before decoding the current one.
• Pipeline: Instruction processing is divided into smaller units that can be executed in parallel using pipelines. Ideally, the pipeline advances one step per cycle, maximizing throughput. Instructions can be decoded in a single pipeline stage, eliminating the need for microcode execution as found in CISC processors.
• Fixed Number of Instruction Cycles: Most RISC instructions execute in a single cycle.
• Registers: RISC architectures feature a large number of general-purpose registers, while CISC architectures often use special-purpose registers. In RISC, any register can hold either data or an address. Registers serve as fast local memory for all data processing operations.
• Load-Store Architecture: The processor operates on data stored in registers. Separate load and store instructions facilitate data transfer between the register bank and external memory. Since memory accesses are relatively slow, separating memory accesses from data processing provides an advantage by allowing data items in the register bank to be used multiple times without requiring repeated memory accesses. In contrast, CISC designs allow data processing operations to directly act on memory.

ARM Feature Improvements over RISC

• Variable Cycle Execution: While many ARM instructions execute in a single cycle, some instructions, such as load-store-multiple instructions, vary in execution cycles depending on the number of registers being transferred. These transfers can occur on sequential memory addresses, improving performance since sequential memory accesses are generally faster than random accesses.
• Inline Barrel Shifter: The inline barrel shifter is a hardware component that preprocesses one of the input registers before it’s used by an instruction. This enhances the capability of many instructions, improving core performance and code density.
• Thumb Instruction Set: ARM has enhanced the processor core by adding a second 16-bit instruction set called Thumb. This allows the ARM core to execute either 16-bit or 32-bit instructions. The 16-bit instructions improve code density by approximately 30% compared to the fixed-length 32-bit instructions.
• Conditional Execution: An instruction is executed only when a specific condition is met. This feature improves performance and code density by reducing the need for branch instructions.
• Enhanced Instructions: Enhanced digital signal processor (DSP) instructions have been added to the standard ARM instruction set to support fast 16x16-bit multiplier operations and saturation. These instructions allow a faster-performing ARM processor to replace traditional combinations of a processor plus a DSP in some cases.

ARM Profiles

ARM offers different profiles, including A Profile, M Profile, and R Profile, catering to various application requirements.