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ARM Exception and Interrupt Controller

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vector table

This ARM tutorial covers ARM exceptions and the interrupt controller.

ARM Vector Table

The following table outlines the ARM vector table:

Exception/InterruptShorthandAddressHigh Address
ResetRESET0x000000000xFFFF0000
Undefined InstructionUNDEF0x000000040xFFFF0004
Software InterruptSWI0x000000080xFFFF0008
Prefetch AbortPABT0x0000000C0xFFFF000C
Data AbortDABT0x000000100xFFFF0010
Reserved-0x000000140xFFFF0014
Interrupt RequestIRQ0x000000180xFFFF0018
Fast Interrupt RequestFIQ0x0000001C0xFFFF001C

RESET

  • Occurs when the processor powers up.
  • Initializes the system and sets up stacks for different processor modes.
  • Highest priority exception.
  • Upon entry into the reset handler, the CPSR (Current Program Status Register) is in SVC (Supervisor) mode, and both IRQ and FIQ bits are set to 1, masking any interrupts.

DATA ABORT

  • Second highest priority.
  • Happens when the processor attempts to read/write to an invalid address or access with incorrect permissions.
  • Upon entry into the Data Abort Handler, IRQs will be disabled (I-bit set to 1), and FIQs will be enabled. This means IRQs are masked, while FIQs remain unmasked.

FIQ

  • Highest priority interrupt.
  • IRQ & FIQs are disabled until the FIQ is handled.

IRQ

  • Second highest priority interrupt.
  • The IRQ handler is entered only if there is no FIQ or Data Abort currently in progress.

Pre-Fetch Abort

  • Similar to a data abort, but happens on address fetch failure.
  • On entry to the handler, IRQs are disabled, but FIQs remain enabled and can occur during a Pre-Fetch abort.

simple interrupt system

SWI

  • A Software Interrupt (SWI) exception occurs when the SWI instruction is executed and none of the other higher-priority exceptions have been flagged.

Undefined Instruction

  • The Undefined Instruction exception occurs when an instruction not in the ARM or Thumb instruction set reaches the execute stage of the pipeline and none of the other exceptions have been flagged.
  • It has the same priority as SWI, as only one can happen at a time. The instruction being executed cannot simultaneously be an SWI instruction and an undefined instruction.

state diagram IRQ

ARM Exception Handling

The following events occur when an exception arises:

  • The CPSR (Current Program Status Register) is stored in the SPSR (Saved Program Status Register) of the exception mode.
  • The PC (Program Counter) is stored in the LR (Link Register) of the exception mode.
  • The Link Register is set to a specific address based on the current instruction. For example, for an ISR (Interrupt Service Routine), LR = last executed instruction + 8.
  • The CPSR is updated to reflect the exception.
  • The PC is set to the address of the exception handler.

7 Types of Exceptions in ARM Architecture

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