M-PHY vs. D-PHY vs. C-PHY: A Detailed Comparison

mipi
phy
d-phy
c-phy
interface

This page compares MIPI M-PHY, D-PHY, and C-PHY, highlighting the key differences between the various MIPI versions.

Introduction

The MIPI Alliance, a group of companies, has released various specifications, including C-PHY, D-PHY, and M-PHY physical layer interfaces. These PHY layers are used in devices like cameras, displays, storage, and RFIC interfaces. All three PHY layers are designed for low power consumption, low pin counts, and minimal interference.

Notably, M-PHY offers support for optical interconnects. The main benefits of these PHY interfaces are high performance, high bandwidth, high scalability, and great flexibility.

M-PHY vs. D-PHY vs. C-PHY Comparison

The following table outlines the key differences between M-PHY, D-PHY, and C-PHY based on their respective specifications (V3.1 for M-PHY, V1.2 for D-PHY, and V1.0 for C-PHY).

ParametersM-PHY (as per V3.1)D-PHY (as per V1.2)C-PHY (as per V1.0)
Clocking schemeEmbedded clock, clock is embedded in the data packetDDR source synchronous clockEmbedded clock
DirectionBidirectionalUnidirectional streaming interfaceUnidirectional
Configuration1 lane per direction, dual simplex, 2 pins each (4 total)1 lane plus clock, simplex, 4 pins1 lane (trio), simplex, 3 pins
Data rate per lane (HS mode)1.25/1.45 Gb/s (HS-G1)
2.5/2.9 Gb/s (HS-G2)
5/5.8 Gb/s (HS-G3)
80 Mbps to 2.5 Gbps (Aggregate)5.7 Gbps (Maximum, Aggregate)
Bandwidth per port (3 or 4 lanes)~ 4 to 18.6 Gb/s (Aggregate BW)Max. ~ 10 Gbps per 4 lane port (Aggregate)Max. ~ 17.1 Gbps per 3 lane port (Aggregate)
Channel compensationEqualizationData skew control relative to clock
Encoding to reduce data toggle rate
Maximum transmitter swing amplitudeSA : 250 mV (Peak), LA : 500 mV (peak)LP : 1300 mV (Peak), HS : 360 mV (peak)LP : 1300 mV (Peak), HS : 425 mV (peak)
Symbol coding8B10BNoneUses encoded data to pack 16/7 i.e. 2.28 bits/symbol over 3-wire trios , Uses 7 symbol to 16 bit mapping