8 to 3 encoder with priority Verilog code
This page of Verilog source code section covers 8 to 3 encoder with priority Verilog code. The block diagram and truth table of 8 to 3 encoder with priority Verilog code is also mentioned.
Block Diagram of 8 to 3 encoder with priority
Truth Table of 8 to 3 encoder with priority
8 to 3 encoder with priority Verilog code
module prio_enco(en, a_in, y_op);
input en;
input [7:0] a_in;
output [2:0] y_op;
reg [2:0] y_op;
always @ (a_in,en)
begin
case (a_in)
8'b00000001: y_op = 3'b000;
8'b0000001x: y_op= 3'b001;
8'b000001xx: y_op= 3'b010;
8'b00001xxx: y_op= 3'b011;
8'b0001xxxx: y_op= 3'b100;
8'b001xxxxx: y_op= 3'b101;
8'b01xxxxxx: y_op= 3'b110;
8'b1xxxxxxx: y_op= 3'b111;
default: y_op=3'bxxx;
endcase
end
endmodule
input en;
input [7:0] a_in;
output [2:0] y_op;
reg [2:0] y_op;
always @ (a_in,en)
begin
case (a_in)
8'b00000001: y_op = 3'b000;
8'b0000001x: y_op= 3'b001;
8'b000001xx: y_op= 3'b010;
8'b00001xxx: y_op= 3'b011;
8'b0001xxxx: y_op= 3'b100;
8'b001xxxxx: y_op= 3'b101;
8'b01xxxxxx: y_op= 3'b110;
8'b1xxxxxxx: y_op= 3'b111;
default: y_op=3'bxxx;
endcase
end
endmodule
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